1. Field of Invention
The invention relates to an anisotropic conductive film (ACF), especially to a composite conductive film that is made by polymers and nanowires.
2. Related Art
In packaging techniques a variety of chip packages has been developed, such as a flip chip and a multi-chip module (MCM). Among them, the flip chip technology uses solder bumps to connect the input/output electrodes of the chip and the substrate. However, a mismatch caused by the difference between the coefficient of thermal expansion (CTE) of the chip and that of the substrate makes the connection unstable. Therefore, a common way to solve this problem is dispensing an underfill between the chip and the substrate after the assembly. Nevertheless, if spacing between the chip and the substrate is limited under 100 μm, the present underfill material will be hard to be filled into the spacing.
The present solutions include: 1. replacing the ball type solder bump with a high aspect ratio copper column to increase the spacing between the chip and the substrate; 2. replacing the ball type solder bump with a conductive polymer bump so that it can be a stress buffer by its low Young's modulus property. However, these two methods both have disadvantages. The copper column applied in the first method has a higher Young's modulus than the solder bump. Therefore it the stress can't be buffered. About the second method, because a current conductive polymer still owns a resistivity ten times larger than metal, it is not suitable to be applied to an advanced and developed flip chip package which has tiny a space and a small electrode area.
A multi-chip module (MCM) is a package where multiple chips, whether they have the same function or not, are packaged on one carrier. Because a MCM owns a faster transmission speed, a shorter transmission path, a better electric performance and a much smaller package size and surface area, it can be applied in all kinds of electric devices, making it a foreseeable mainstream product.
There are two kinds of MCM, a 2 dimensions MCM (2D MCM) and a 3 dimensions MCM (3D MCM). A 3D MCM has a better miniaturization outcome than a 2D MCM. Therefore it has become a major development topic in recent years. The solder bump used in a flip chip also can be used in a 3D MCM for chip to chip stacking or for chip stacking by an interposer. Nevertheless, the thickness obtained by applying these two packaging techniques still is thicker in application. Therefore, another method uses a metal electrode of the input/output electrodes (such as a copper of a copper chip) instead of the carriers and the solder bumps, to stack the provided chips. The thickness of chip used in this kind of technology can be less than 30 μm, therefore more than 10 layers can be stacked together to become a system on chip (SOC). Except for increasing the functions and providing miniaturization, this method can reduce the numbers of input/output terminals between the chip and the substrate. Therefore the substrate area and the required number of layers can be reduced, cutting down the overall cost.
However, the 3D stack package has the following problems: 1. lower stability, caused by the higher temperature and pressure used in a metal diffusion bonding process; 2. extra protection, required for preventing the thin chip from damage; 3. chips with different functions, having different input/output positions; 4. smaller spacing for input/output terminals, because the increased numbers of input/output terminals, when connecting multilayer chips; and 5. heat dissipation.
U.S. Pat. No. 6,849,802 provides a chip stack package where the original input/output are rewired to the edge of the bare chip, to be the connection members between the two stacked chips, and a conductive adhesive is used between the two chips to form a vertical electrical connection. Therefore, the original input/output between chips can still be electrically connected by conductive bumps. Nevertheless, rewiring the input/output to the edge of the bare chip may cause a decrease of the spacing for the input/output and decrease in the area for the input/output and therefore the difficulties of bonding process in chip stacking increase. Moreover, the sidewall conductive adhesive used in the chip stack package for stabilizing the structure generally has a large contacting resistance with the metal joint. Therefore it hardly satisfies the high speed requirement of an advanced chip.
Accordingly, a low resistance anisotropic conductive film, which is suitable for tiny spacing and for applying a low temperature and low pressure bonding process is developed.